Semiconductor wafers or other such substrates are subjected to very high processing temperatures. For example, in high temperature epitaxial chemical vapor deposition (CVD), the temperatures can approach 1200° C., while low temperature epitaxy is conducted between about 400° C. and 900° C. In a typical cycle, using one or more robotic wafer handlers, a wafer is transferred from a room temperature cassette either directly, or via one or more loadlock and transfer chambers, into a processing or reaction chamber where the wafer is subjected to high temperature processing. The wafer is then transferred using one or more wafer handlers from the high temperature processing chamber back to the same cassette or a separate cassette for processed wafers, either directly from the processing chamber or via the loadlock and transfer chambers.
Because of the high temperature CVD processing, transport of the wafer from the process chamber immediately to, e.g., a wafer cassette is not possible due to the temperature of the wafer exceeding the limits of heat resistance of the materials commonly used in the cassettes. At these temperatures, the cassettes may be damaged and the structural integrity of the cassette may be undermined. Because of this, transfer of the wafer to the cassette must be postponed until the wafer temperature falls below the limits of the thermal materials properties of the cassette material. While cassettes are available that can handle wafers as hot as 170° C., they are relatively expensive. A commonly available and less expensive cassette made of Delrin® can only handle temperatures well below 100° C. Other commonly available units can only accomodate wafer temperatures of about 60° C.
Similarly, transfer of the wafers to a loadlock chamber immediately after high temperature processing is not possible because the temperature of a just-processed wafer  may exceed the limits of the heat resistance of materials typically used to support the wafers in a loadlock. As such, the structural integrity of the wafer support devices in the loadlock chamber may be undermined and the loadlock may be damaged. Consequently, it is necessary to cool the temperature of the wafer to levels suitable for contact with the surfaces of a cassette or a loadlock.
Because wafer handling and processing typically occur in an enclosed and carefully controlled environment, there are three principle locations or points during the cycle where the cooling of the wafer might occur: the wafer could be cooled on the susceptor on which it is supported in the process chamber, on the wafer handling device, or off-line at some location within the apparatus between the process chamber and the cassette or loadlock. Cooling the wafer on the susceptor is not cost-effective, however, because the process chamber is then unavailable for processing another wafer, thereby reducing the system wafer throughput. This approach is particularly unattractive because it is then necessary to incur the delay and cost of reheating the wafer support structure or the chamber generally (in the case of hot wall chambers). Removing a wafer while it is hot and cooling it on the wafer handling device is better, but also not cost effective because the delay in loading the next wafer slated for processing also compromises throughput, or requires additional wafer handling equipment and room for accommodating the same. Such impediments increase the per-wafer cost, making these approaches financially unattractive to end users. Because of the high cost of semiconductor wafer processing equipment, it is, of course, critically important from a competitive standpoint to be able to keep this expensive processing equipment in continued use so as to increase the throughput. At the same time, the wafer cooling technique employed must be compatible with the environment of the CVD processing apparatus so as not to adversely affect stringent cleanliness requirements. Also, the cost of the technique must itself be sufficiently moderate so that there is a net reduction in per-wafer costs.
Use of off-line cooling chambers for cooling a wafer can be more efficient, since the susceptor and wafer handling device are not occupied by the wafer being cooled. In conventional cooling chambers, a wafer is positioned on pins in the chamber and cooled by conduction or convection, e.g., by flowing cooling gases over the surfaces of the wafer.  Because of the high temperature of the wafer, these pins are typically constructed of quartz or silicon carbide. This approach to cooling wafers also has drawbacks, however, as the relatively hard pins can damage and leave scratches on the backside, or bottom surface, of the wafers by the force of the wafers being placed upon the pins. In addition, contraction of a wafer while it cools on the pins can further scratch the wafer.
Accordingly, it is an object of this invention to provide an improved system for quickly cooling wafer-like substrates to a temperature that will allow the use of low cost commonly available cassettes, while not causing damage to the bottom surface of the wafer.